 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| ESMT Flash FEATURES Single supply voltage 2.7~3.6V Standard, Dual SPI Speed - Read max frequency: 33MHz - Fast Read max frequency: 50MHz; 100MHz - Fast Read Dual max frequency: 50MHz / 100MHz (100MHz / 200MHz equivalent Dual SPI) Low power consumption - Active current: 35 mA - Standby current: 30 A Reliability - 100,000 typical program/erase cycles - 20 years Data Retention Program - Byte programming time: 7 s (typical) - Page programming time: 1.5 ms (typical) Erase - Chip erase time 10 sec (typical) - Block erase time 1 sec (typical) - Sector erase time 90 ms (typical) Page Programming - 256 byte per programmable page F25L16PA 3V Only 16 Mbit Serial Flash Memory with Dual Auto Address Increment (AAI) WORD Programming - Decrease total chip programming time over Byte Program operations Lockable 4K bytes OTP security sector SPI Serial Interface - SPI Compatible: Mode 0 and Mode 3 End of program or erase detection Write Protect ( WP ) Hold Pin ( HOLD ) All Pb-free products are RoHS-Compliant ORDERING INFORMATION Product ID F25L16PA -50PG F25L16PA -100PG F25L16PA -50PAG F25L16PA -100PAG F25L16PA -50DG F25L16PA -100DG Speed 50MHz Package 8 lead SOIC 150mil 150mil 200mil 200mil 300mil 300mil Comments Pb-free Pb-free Pb-free Pb-free Pb-free Pb-free 100MHz 8 lead SOIC 50MHz 8 lead SOIC 100MHz 8 lead SOIC 50MHz 100MHz 8 lead PDIP 8 lead PDIP GENERAL DESCRIPTION The F25L16PA is a 16Megabit, 3V only CMOS Serial Flash memory device. The device supports the standard Serial Peripheral Interface (SPI), and a Dual SPI. ESMT's memory devices reliably store memory data even after 100,000 programming and erase cycles. The memory array can be organized into 8,192 programmable pages of 256 byte each. 1 to 256 byte can be programmed at a time with the Page Program instruction. The device also can be programmed to decrease total chip programming time with Auto Address Increment (AAI) programming. The device features sector erase architecture. The memory array is divided into 512 uniform sectors with 4K byte each; 32 uniform blocks with 64K byte each. Sectors can be erased individually without affecting the data in other sectors. Blocks can be erased individually without affecting the data in other blocks. Whole chip erase capabilities provide the flexibility to revise the data in the device. The device has Sector, Block or Chip Erase but no page erase. The sector protect/unprotect feature disables both program and erase operations in any combination of the sectors of the memory. Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2009 Revision: 1.4 1/33 ESMT PIN CONFIGURATIONS F25L16PA 8-PIN SOIC CE 1 8 VDD SO 2 3 7 6 HOLD SCK WP VSS 4 5 SI 8-PIN PDIP CE 1 8 VDD SO 2 3 7 6 HOLD SCK WP VSS 4 5 SI Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2009 Revision: 1.4 2/33 ESMT PIN DESCRIPTION Symbol SCK SI Pin Name Serial Clock Serial Data Input Functions To provide the timing for serial input and output operations To transfer commands, addresses or data serially into the device. Data is latched on the rising edge of SCK. To transfer data serially out of the device. Data is shifted out on the falling edge of SCK. To activate the device when CE is low. The Write Protect ( WP ) pin is used to enable/disable BPL bit in the status register. To temporality stop serial communication with SPI flash memory without resetting the device. To provide power. F25L16PA SO CE WP Serial Data Output Chip Enable Write Protect HOLD VDD VSS Hold Power Supply Ground FUNCTIONAL BLOCK DIAGRAM Address Buffers and Latches X-Decoder Flash Y-Decoder Control Logic I/O Butters and Data Latches Serial Interface CE SCK SI SO WP HOLD Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2009 Revision: 1.4 3/33 ESMT SECTOR STRUCTURE Table 1: F25L16PA Sector Address Table Block Sector 511 31 : 496 495 30 : 480 479 29 : 464 463 28 : 448 447 27 : 432 431 26 : 416 415 25 : 400 399 24 : 384 383 23 : 368 367 22 : 352 351 21 : 336 335 20 : 320 319 19 : 304 Sector Size (Kbytes) 4KB : 4KB 4KB : 4KB 4KB : 4KB 4KB : 4KB 4KB : 4KB 4KB : 4KB 4KB : 4KB 4KB : 4KB 4KB : 4KB 4KB : 4KB 4KB : 4KB 4KB : 4KB 4KB : 4KB Address range 1FF000H - 1FFFFFH : 1F0000H - 1F0FFFH 1EF000H - 1EFFFFH : 1E0000H - 1E0FFFH 1DF000H - 1DFFFFH : 1D0000H - 1D0FFFH 1CF000H - 1CFFFFH : 1C0000H - 1C0FFFH 1BF000H - 1BFFFFH : 1B0000H - 1B0FFFH 1AF000H - 1AFFFFH : 1A0000H - 1A0FFFH 19F000H - 19FFFFH : 190000H - 190FFFH 18F000H - 18FFFFH : 180000H - 180FFFH 17F000H - 17FFFFH : 170000H - 170FFFH 16F000H - 16FFFFH : 160000H - 160FFFH 15F000H - 15FFFFH : 150000H - 150FFFH 14F000H - 14FFFFH : 140000H - 140FFFH 13F000H - 13FFFFH : 130000H - 130FFFH 1 0 0 1 0 1 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1 1 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 F25L16PA Block Address A20 A19 A18 A17 1 A16 1 1 0 0 1 0 0 1 1 1 0 0 1 0 0 1 1 1 0 0 1 0 0 1 1 Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2009 Revision: 1.4 4/33 ESMT Table 1: F25L16PA Sector Address Table - continued I Sector Size (Kbytes) 4KB : 4KB 4KB : 4KB 4KB : 4KB 4KB : 4KB 4KB : 4KB 4KB : 4KB 4KB : 4KB 4KB : 4KB 4KB : 4KB 4KB : 4KB 4KB : 4KB 4KB : 4KB 4KB : 4KB Block Sector 303 18 : 288 287 17 : 272 271 16 : 256 255 15 : 240 239 14 : 224 223 13 : 208 207 12 : 192 191 11 : 176 175 10 : 160 159 9 : 144 143 8 : 128 127 7 : 112 111 6 : 96 Address range 12F000H - 12FFFFH : 120000H - 120FFFH 11F000H - 11FFFFH : 110000H - 110FFFH 10F000H - 10FFFFH : 100000H - 100FFFH 0FF000H - 0FFFFFH : 0F0000H - 0F0FFFH 0EF000H - 0EFFFFH : 0E0000H - 0E0FFFH 0DF000H - 0DFFFFH : 0D0000H - 0D0FFFH 0CF000H - 0CFFFFH : 0C0000H - 0C0FFFH 0BF000H - 0BFFFFH : 0B0000H - 0B0FFFH 0AF000H - 0AFFFFH : 0A0000H - 0A0FFFH 09F000H - 09FFFFH : 090000H - 090FFFH 08F000H - 08FFFFH : 080000H - 080FFFH 07F000H - 07FFFFH : 070000H - 070FFFH 06F000H - 06FFFFH : 060000H - 060FFFH 0 0 1 0 0 1 0 1 0 0 1 0 0 1 0 0 1 0 0 1 1 0 1 1 0 1 1 0 1 1 1 0 0 1 0 0 1 0 0 A20 A19 F25L16PA Block Address A18 A17 1 A16 0 0 1 0 0 1 1 1 0 0 1 0 0 1 1 1 0 0 1 0 0 1 1 1 0 Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2009 Revision: 1.4 5/33 ESMT Table 1: F25L16PA Sector Address Table - continued II Block Sector 95 5 : 80 79 4 : 64 63 3 : 48 47 2 : 32 31 1 : 16 15 0 : 0 Sector Size (Kbytes) 4KB : 4KB 4KB : 4KB 4KB : 4KB 4KB : 4KB 4KB : 4KB 4KB : 4KB Address range 05F000H - 05FFFFH : 050000H - 050FFFH 04F000H - 04FFFFH : 040000H - 040FFFH 03F000H - 03FFFFH : 030000H - 030FFFH 02F000H - 02FFFFH : 020000H - 020FFFH 01F000H - 01FFFFH : 010000H - 010FFFH 00F000H - 00FFFFH : 000000H - 000FFFH 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 A20 A19 F25L16PA Block Address A18 A17 0 A16 1 0 0 1 1 1 0 0 1 0 0 STATUS REGISTER The software status register provides status on whether the flash memory array is available for any Read or Write operation, whether the device is Write enabled, and the state of the memory Write protection. During an internal Erase or Program operation, the status register may be read only to determine the completion of an operation in progress. Table 2 describes the function of each bit in the software status register. Table 2: Software Status Register Bit 0 1 2 3 4 5 6 7 Note: 1. Only BP0, BP1, BP2 and BPL are writable. 2. All register bits are volatility 3. All area are protected at power-on (BP2=BP1=BP0=1) Name BUSY WEL BP0 BP1 BP2 RESERVED AAI BPL Function 1 = Internal Write operation is in progress 0 = No internal Write operation is in progress 1 = Device is memory Write enabled 0 = Device is not memory Write enabled Indicate current level of block write protection (See Table 3) Indicate current level of block write protection (See Table 3) Indicate current level of block write protection (See Table 3) Reserved for future use Auto Address Increment Programming status 1 = AAI programming mode 0 = Page Program mode 1 = BP2,BP1,BP0 are read-only bits 0 = BP2,BP1,BP0 are read/writable Default at Power-up 0 0 1 1 1 0 0 0 Read/Write R R R/W R/W R/W N/A R R/W Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2009 Revision: 1.4 6/33 ESMT WRITE ENABLE LATCH (WEL) The Write-Enable-Latch bit indicates the status of the internal memory Write Enable Latch. If this bit is set to "1", it indicates the device is Write enabled. If the bit is set to "0" (reset), it indicates the device is not Write enabled and does not accept any memory Write (Program/ Erase) commands. This bit is automatically reset under the following conditions: * * * * * * * * Power-up Write Disable (WRDI) instruction completion Page Program instruction completion Auto Address Increment (AAI) Programming is completed and reached its highest unprotected memory address Sector Erase instruction completion Block Erase instruction completion Chip Erase instruction completion Write Status Register instructions F25L16PA BUSY The BUSY bit determines whether there is an internal Erase or Program operation in progress. A "1" for the BUSY bit indicates the device is busy with an operation in progress. A "0" indicates the device is ready for the next valid operation. Auto Address Increment (AAI) The Auto-Address-Increment-Programming-Status bit provides status on whether the device is in AAI Programming mode or Page Program mode. The default at power up is Page Program mode. Table 3: F25L16PA Block Protection Table Protection Level 0 Upper 1/32 Upper 1/16 Upper 1/8 Upper 1/4 Upper 1/2 All Blocks All Blocks 0 0 0 0 1 1 1 1 Status Register Bit BP2 BP1 0 0 1 1 0 0 1 1 BP0 0 1 0 1 0 1 0 1 Protected Memory Area Block Range None Block 31 Block 30~31 Block 28~31 Block 24~31 Block 16~31 Block 0~31 Block 0~31 Address Range None 1F0000H - 1FFFFFH 1E0000H - 1FFFFFH 1C0000H - 1FFFFFH 180000H - 1FFFFFH 100000H - 1FFFFFH 000000H - 1FFFFFH 000000H - 1FFFFFH Block Protection (BP2, BP1, BP0) The Block-Protection (BP2, BP1, BP0) bits define the size of the memory area, as defined in Table 3, to be software protected against any memory Write (Program or Erase) operations. The Write Status Register (WRSR) instruction is used to program the BP2, BP1, BP0 bits as long as WP is high or the BlockProtection-Look (BPL) bit is 0. Chip Erase can only be executed if Block-Protection bits are all 0. After power-up, BP2, BP1 and BP0 are set to1. Block Protection Lock-Down (BPL) WP pin driven low (VIL), enables the Block-ProtectionLock-Down (BPL) bit. When BPL is set to 1, it prevents any further alteration of the BPL, BP2, BP1, and BP0 bits. When the WP pin is driven high (VIH), the BPL bit has no effect and its value is "Don't Care". After power-up, the BPL bit is reset to 0. Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2009 Revision: 1.4 7/33 ESMT HOLD OPERATION HOLD pin is used to pause a serial sequence underway with the SPI flash memory without resetting the clocking sequence. To activate the HOLD mode, CE must be in active low state. The HOLD mode begins when the SCK active low state coincides with the falling edge of the HOLD signal. The HOLD mode ends when the HOLD signal's rising edge coincides with the SCK active low state. If the falling edge of the HOLD signal does not coincide with the SCK active low state, then the device enters Hold mode when the SCK next reaches the active low state. Similarly, if the rising edge of the HOLD signal does not coincide with the SCK active low state, then the device exits in F25L16PA Hold mode when the SCK next reaches the active low state. See Figure 1 for Hold Condition waveform. Once the device enters Hold mode, SO will be in high impedance state while SI and SCK can be VIL or VIH. If CE is driven active high during a Hold condition, it resets the internal logic of the device. As long as HOLD signal is low, the memory remains in the Hold condition. To resume communication with the device, HOLD must be driven active high, and CE must be driven active low. See Figure 23 for Hold timing. S CK HO L D A ctive Ho ld A ctive Ho ld A ctive Figure 1: HOLD Condition Waveform WRITE PROTECTION F25L16PA provides software Write Protection. The Write-Protect pin ( WP ) enables or disables the lock-down function of the status register. The Block-Protection bits (BP2, BP1, BP0, and BPL) in the status register provide Write protection to the memory array and the status register. See Table 4 for Block-Protection description. Table 4: Conditions to Execute Write-Status-Register (WRSR) Instruction WP BPL 1 0 X Execute WRSR Instruction Not Allowed Allowed Allowed L L H Write Protect Pin ( WP ) The Write-Protect ( WP ) pin enables the lock-down function of the BPL bit (bit 7) in the status register. When WP is driven low, the execution of the Write Status Register (WRSR) instruction is determined by the value of the BPL bit (see Table 4). When WP is high, the lock-down function of the BPL bit is disabled. Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2009 Revision: 1.4 8/33 ESMT INSTRUCTIONS Instructions are used to Read, Write (Erase and Program), and configure the F25L16PA. The instruction bus cycles are 8 bits each for commands (Op Code), data, and addresses. Prior to executing any Page Program, Auto Address Increment (AAI) Programming, Write Status Register, Sector Erase, Block Erase, or Chip Erase instructions, the Write Enable (WREN) instruction must be executed first. The complete list of the instructions is provided in Table 5. All instructions are synchronized off a high to low transition of CE . Inputs will be accepted on the rising edge of SCK starting with the most significant bit. CE must be driven F25L16PA low before an instruction is entered and must be driven high after the last bit of the instruction has been shifted in (except for Read, Read ID, Read Status Register, Read Electronic Signature instructions). Any low to high transition on CE , before receiving the last bit of an instruction bus cycle, will terminate the instruction in progress and return the device to the standby mode. Instruction commands (Op Code), addresses, and data are all input from the most significant bit (MSB) first. Table 5: Device Operation Instructions Operation Read Fast Read Fast Read Dual 12,13 Output Sector Erase4 (4K Byte) Block Erase4, (64K Byte) Chip Erase Page Program (PP) Max. Freq Bus Cycle 1~3 4 SOUT SIN SOUT SIN SOUT SIN Hi-Z A15-A8 Hi-Z A7-A0 Hi-Z X Hi-Z A15-A8 Hi-Z A7-A0 Hi-Z X 3 A15-A8 A7-A0 DIN0 DIN0 X X - 1 2 SOUT SIN Hi-Z A23-A16 Hi-Z A23-A16 5 SOUT DOUT0 X X Hi-Z Hi-Z 8CH 14H DIN1 DIN1 X X SIN X X 6 SOUT DOUT1 DOUT0 Hi-Z Hi-Z 14H 8CH SIN N SOUT SIN 33 MHz 03H 0BH 20H D8H 60H / C7H 02H X X - cont. cont. - 3BH A23-A16 DOUT0~1 cont. Hi-Z A23-A16 Hi-Z A15-A8 Hi-Z A7-A0 Hi-Z Hi-Z A23-A16 Hi-Z A15-A8 Hi-Z A7-A0 Hi-Z Hi-Z - Hi-Z A23-A16 Hi-Z A15-A8 Hi-Z A7-A0 Hi-Z Hi-Z A23-A16 Hi-Z A15-A8 Hi-Z A7-A0 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z X DIN X X X X 00H DOUT Hi-Z 14H 34H 74H 8CH Hi-Z X 00H 20H Hi-Z -. -. -. -. X 00H 01H 15H Hi-Z Hi-Z - Up to 256 Hi-Z bytes - Auto Address Increment ADH 5 word programming (AAI) Read Status Register 05H 6 (RDSR) Enable Write Status 50H 7 Register (EWSR) 50MHz Write Status Register 01H 7 (WRSR) 10 Write Enable (WREN) 06H Write Disable (WRDI)/ 04H Exit secured OTP mode Enter secured OTP mode B1H (ENSO) 100MHz Read Electronic ABH 8 Signature (RES) RES in secured OTP ABH mode & not lock down RES in secured OTP ABH mode & lock down Jedec Read ID 9FH 9 (JEDEC-ID) Read ID (RDID) 11 Enable SO to output RY/ Status during AAI (EBSY) Disable SO to output Status during AAI RY/ (DBSY) 90H 70H 80H Hi-Z - - - - - - - - - - - - Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2009 Revision: 1.4 9/33 ESMT Note: F25L16PA 1. Operation: SIN = Serial In, SOUT = Serial Out, Bus Cycle 1 = Op Code 2. X = Dummy Input Cycles (VIL or VIH); - = Non-Applicable Cycles (Cycles are not necessary); cont. = continuous 3. One bus cycle is eight clock periods. 4. Sector Earse addresses: use AMS -A12, remaining addresses can be VIL or VIH Block Earse addresses: use AMS -A16, remaining addresses can be VIL or VIH 5. To continue programming to the next sequential address location, enter the 8-bit command, followed by the data to be programmed. 6. The Read-Status-Register is continuous with ongoing clock cycles until terminated by a low to high transition on CE . 7. The Enable-Write-Status-Register (EWSR) instruction and the Write-Status-Register (WRSR) instruction must work in conjunction of each other. The WRSR instruction must be executed immediately (very next bus cycle) after the EWSR instruction to make both instructions effective. 8. The Read-Electronic-Signature is continuous with on going clock cycles until terminated by a low to high transition on CE . 9. The Jedec-Read-ID is output first byte 8CH as manufacture ID; second byte 20H as top memory type; third byte 15H as memory capacity. 10. The Write-Enable (WREN) instruction and the Write-Status-Register (WRSR) instruction must work in conjunction of each other. The WRSR instruction must be executed immediately (very next bus cycle) after the WREN instruction to make both instructions effective. Both EWSR and WREN can enable WRSR, user just need to execute one of it. A successful WRSR can reset WREN. 11. The Manufacture ID and Device ID output will repeat continuously until CE terminates the instruction. 12. Dual commands use bidirectional IO pins. DOUT and cont. are serial data out; others are serial data in. 13. Dual output data: IO0 = (D6, D4, D2, D0), (D6, D4, D2, D0) IO1 = (D7, D5, D3, D1), (D7, D5, D3, D1) DOUT0 DOUT1 Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2009 Revision: 1.4 10/33 ESMT Read (33MHz) The Read instruction supports up to 33 MHz, it outputs the data starting from the specified address location. The data output stream is continuous through all addresses until terminated by a low to high transition on CE . The internal address pointer will automatically increment until the highest memory address is reached. Once the highest memory address is reached, the address pointer will automatically increment to the beginning (wrap-around) of the address space, i.e. for 16Mbit density, once F25L16PA the data from address location 1FFFFFH had been read, the next output will be from address location 000000H. The Read instruction is initiated by executing an 8-bit command, 03H, followed by address bits [A23 -A0]. CE must remain active low for the duration of the Read cycle. See Figure 2 for the Read sequence. Figure 2: Read Sequence Fast Read (50 MHz; 100 MHz) The Fast Read instruction supporting up to 100 MHz is initiated by executing an 8-bit command, 0BH, followed by address bits [A23 -A0] and a dummy byte. CE must remain active low for the duration of the Fast Read cycle. See Figure 3 for the Fast Read sequence. Following a dummy byte (8 clocks input dummy cycle), the Fast Read instruction outputs the data starting from the specified address location. The data output stream is continuous through all addresses until terminated by a low to high transition on CE . The internal address pointer will automatically increment until the highest memory address is reached. Once the highest memory address is reached, the address pointer will automatically increment to the beginning (wrap-around) of the address space, i.e. for 16Mbit density, once the data from address location 1FFFFFH has been read, the next output will be from address location 000000H. CE MODE3 SCK MODE0 012345678 15 16 23 24 31 32 39 40 47 48 55 56 63 64 71 72 80 SI MSB 0B ADD. MSB HIGH IMPENANCE ADD. ADD. X N DOUT MSB N+1 DOUT N+2 DOUT N+3 DOUT N+4 DOUT SO Note : X = Dummy Byte : 8 Clocks Input Dummy (VIL or VIH) Figure 3: Fast Read Sequence Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2009 Revision: 1.4 11/33 ESMT Fast Read Dual Output (50 MHz; 100 MHz) The Fast Read Dual Output (3BH) instruction is similar to the standard Fast Read (0BH) instruction except the data is output on SI and SO pins. This allows data to be transferred from the device at twice the rate of standard SPI devices. This instruction is for quickly downloading code from Flash to RAM upon power-up or for applications that cache code- segments to RAM for execution. F25L16PA The Fast Read Dual Output instruction is initiated by executing an 8-bit command, 3BH, followed by address bits [A23 -A0] and a dummy byte. CE must remain active low for the duration of the Fast Read Dual Output cycle. See Figure 4 for the Fast Read Dual Output sequence. Figure 4: Fast Read Dual Output Sequence Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2009 Revision: 1.4 12/33 ESMT Page Program (PP) The Page Program instruction allows many bytes to be programmed in the memory. The bytes must be in the erased state (FFH) when initiating a Program operation. A Page Program instruction applied to a protected memory area will be ignored. Prior to any Write operation, the Write Enable (WREN) instruction must be executed. CE must remain active low for the duration of the Page Program instruction. The Page Program instruction is initiated by executing an 8-bit command, 02H, followed by address bits [A23-A0]. Following the address, at least one byte Data is input (the maximum of input data can be up to 256 bytes). If the 8 least significant address bits [A7-A0] are not all zero, all transmitted data that goes beyond the end of the current page are programmed from the start address of the same page (from the address whose 8 least significant bits [A7-A0] are all zero). If more than 256 bytes Data are sent to the device, previously F25L16PA latched data are discarded and the last 256 bytes Data are guaranteed to be programmed correctly within the same page. If less than 256 bytes Data are sent to device, they are correctly programmed at the requested addresses without having any effects on the other bytes of the same page. CE must be driven high before the instruction is executed. The user may poll the BUSY bit in the software status register or wait TPP for the completion of the internal self-timed Page Program operation. While the Page Program cycle is in progress, the Read Status Register instruction may still be accessed for checking the status of the BUSY bit. It is recommended to wait for a duration of TBP1 before reading the status register to check the BUSY bit. The BUSY bit is a 1 during the Page Program cycle and becomes a 0 when the cycle is finished and the device is ready to accept other instructions again. After the Page Program cycle has finished, the Write-Enable-Latch (WEL) bit in the Status Register is cleared to 0. See Figure 5 for the Page Program sequence. Figure 5: Page Program Sequence Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2009 Revision: 1.4 13/33 ESMT Auto Address Increment (AAI) WORD Program The AAI program instruction allows multiple bytes of data to be programmed without re-issuing the next sequential address location. This feature decreases total programming time when the multiple bytes or entire memory array is to be programmed. An AAI program instruction pointing to a protected memory area will be ignored. The selected address range must be in the erased state (FFH) when initiating an AAI program instruction. While within AAI WORD programming sequence, the only valid instructions are AAI WORD program operation, RDSR, WRDI. Users have three options to determine the completion of each AAI WORD program cycle: hardware detection by reading the SO; software detection by polling the BUSY in the software status register or wait TBP. Refer to End of Write Detection section for details. Prior to any write operation, the Write Enable (WREN) instruction must be executed. The AAI WORD program instruction is initiated by executing an 8-bit command, ADH, followed by address bits [A23 -A0]. Following the addresses, two bytes of data is input sequentially. The data is input sequentially from MSB (bit F25L16PA 7) to LSB (bit 0). The first byte of data (D0) will be programmed into the initial address [A23 -A1] with A0 =0; the second byte of data (D1) will be programmed into the initial address [A23 -A1] with A0 =1. CE must be driven high before the AAI WORD program instruction is executed. The user must check the busy status before entering the next valid command. Once the device indicates it is no longer busy, data for next two sequential addresses may be programmed and so on. When the last desired byte had been entered, check the busy status using the hardware method or the RDSR instruction and execute the WRDI instruction, to terminate AAI. User must check busy status after WRDI to determine if the device is ready for any command. Please refer to Figure 8 and Figure 9. There is no wrap mode during AAI programming; once the highest unprotected memory address is reached, the device will exit AAI operation and reset the Write-Enable-Latch bit (WEL = 0) and the AAI bit (AAI=0). End of Write Detection There are three methods to determine completion of a program cycle during AAI WORD programming: hardware detection by reading the SO, software detection by polling the BUSY bit in the Software Status Register or wait TBP. The Hardware End of Write Detection method is described in the section below. Hardware End of Write Detection The Hardware End of Write Detection method eliminates the overhead of polling the BUSY bit in the Software Status Register during an AAI Word program operation. The 8-bit command, 70H, configures the SO pin to indicate Flash busy status during AAI WORD programming (refer to Figure 6). The 8-bit command, 70H, must be executed prior to executing an AAI WORD program instruction. Once an internal programming operation begins, asserting CE will immediately drive the status of the internal flash status on the SO pin. A "0" Indicates the device is busy; a "1" Indicates the device is ready for the next instruction. De-asserting CE will return the SO pin to tri-state. The 8-bit command, 80H, disables the SO pin to output busy status during AAI WORD program operation and return SO pin to output Software Status Register data during AAI WORD programming (refer to Figure 7). Figure 6: Enable SO as Hardware RY/ BY during AAI Programming Figure 7: Disable SO as Hardware RY/ BY during AAI Programming Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2009 Revision: 1.4 14/33 ESMT F25L16PA Figure 8: AAI Word Program Sequence with Hardware End of Write Detection Figure 9: AAI Word Program Sequence with Software End of Write Detection Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2009 Revision: 1.4 15/33 ESMT 64K Byte Block Erase The 64K-byte Block Erase instruction clears all bits in the selected block to FFH. A Block Erase instruction applied to a protected memory area will be ignored. Prior to any Write operation, the Write Enable (WREN) instruction must be executed. CE must remain active low for the duration of the any command sequence. The Block Erase instruction is initiated by executing an 8-bit command, D8H, followed by address bits [A23 F25L16PA -A0]. Address bits [AMS -A16] (AMS = Most Significant address) are used to determine the block address (BAX), remaining address bits can be VIL or VIH. CE must be driven high before the instruction is executed. The user may poll the BUSY bit in the Software Status Register or wait TBE for the completion of the internal self-timed Block Erase cycle. See Figure 10 for the Block Erase sequence. Figure 10: 64K-byte Block Erase Sequence 4K Byte Sector Erase The Sector Erase instruction clears all bits in the selected sector to FFH. A Sector Erase instruction applied to a protected memory area will be ignored. Prior to any Write operation, the Write Enable (WREN) instruction must be executed. CE must remain active low for the duration of the any command sequence. The Sector Erase instruction is initiated by executing an 8-bit command, 20H, followed by address bits [A23 -A0]. Address bits [AMS -A12] (AMS = Most Significant address) are used to determine the sector address (SAX), remaining address bits can be VIL or VIH. CE must be driven high before the instruction is executed. The user may poll the BUSY bit in the Software Status Register or wait TSE for the completion of the internal self-timed Sector Erase cycle. See Figure 11 for the Sector Erase sequence. CE MODE3 SCK MODE0 012345678 15 16 23 24 31 SI MSB 20 ADD. MSB HIGH IMPENANCE ADD. ADD. SO Figure 11: Sector Erase Sequence Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2009 Revision: 1.4 16/33 ESMT Chip Erase The Chip Erase instruction clears all bits in the device to FFH. A Chip Erase instruction will be ignored if any of the memory area is protected. Prior to any Write operation, the Write Enable (WREN) instruction must be executed. CE must remain active low for the duration of the Chip-Erase instruction sequence. The Chip F25L16PA Erase instruction is initiated by executing an 8-bit command, 60H or C7H. CE must be driven high before the instruction is executed. The user may poll the BUSY bit in the Software Status Register or wait TCE for the completion of the internal self-timed Chip Erase cycle. See Figure 12 for the Chip Erase sequence. CE MODE3 SCK MODE0 01234567 SI MSB 60 or C7 SO HIGH IMPENANCE Figure 12: Chip Erase Sequence Read Status Register (RDSR) The Read Status Register (RDSR) instruction allows reading of the status register. The status register may be read at any time even during a Write (Program/Erase) operation. When a Write operation is in progress, the BUSY bit may be checked before sending any new commands to assure that the new commands are properly received by the device. CE must be driven low before the RDSR instruction is entered and remain low until the status data is read. Read Status Register is continuous with ongoing clock cycles until it is terminated by a low to high transition of the CE . See Figure 13 for the RDSR instruction sequence. Figure 13: Read Status Register (RDSR) Sequence Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2009 Revision: 1.4 17/33 ESMT Write Enable (WREN) The Write Enable (WREN) instruction sets the Write-EnableLatch bit in the Software Status Register to 1 allowing Write operations to occur. The WREN instruction must be executed prior to any Write F25L16PA (Program/Erase) operation. CE must be driven high before the WREN instruction is executed. CE MODE3 SCK MODE0 01234567 SI MSB 06 SO HIGH IMPENANCE Figure 14: Write Enable (WREN) Sequence Write Disable (WRDI) The Write Disable (WRDI) instruction resets the Write-EnableLatch bit to 0 disabling any new Write operations from occurring or exits from OTP mode to normal mode. CE must be driven high before the WRDI instruction is executed. CE MODE3 SCK MODE0 01234567 SI MSB 04 SO HIGH IMPENANCE Figure 15: Write Disable (WRDI) Sequence Enable Write Status Register (EWSR) The Enable Write Status Register (EWSR) instruction arms the Write Status Register (WRSR) instruction and opens the status register for alteration. The Enable Write Status Register instruction does not have any effect and will be wasted, if it is not followed immediately by the Write Status Register (WRSR) instruction. CE must be driven low before the EWSR instruction is entered and must be driven high before the EWSR instruction is executed. Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2009 Revision: 1.4 18/33 ESMT Write Status Register (WRSR) The Write Status Register instruction writes new values to the BP2, BP1, BP0, and BPL bits of the status register. CE must be driven low before the command sequence of the WRSR instruction is entered and driven high before the WRSR instruction is executed. See Figure 16 for EWSR or WREN and WRSR instruction sequences. Executing the Write Status Register instruction will be ignored when WP is low and BPL bit is set to "1". When the WP is low, the BPL bit can only be set from "0" to "1" to lock down the status register, but cannot be reset from "1" to "0". F25L16PA When WP is high, the lock-down function of the BPL bit is disabled and the BPL, BP0, BP1,and BP2 bits in the status register can all be changed. As long as BPL bit is set to 0 or WP pin is driven high (VIH) prior to the low-to-high transition of the CE pin at the end of the WRSR instruction, the bits in the status register can all be altered by the WRSR instruction. In this case, a single WRSR instruction can set the BPL bit to "1" to lock down the status register as well as altering the BP0; BP1 and BP2 bits at the same time. See Table 4 for a summary description of WP and BPL functions. CE MODE3 SCK MODE0 STATUS REGISTER IN 76543210 01234567 0 1 2 3 4 5 6 7 8 9 1011 12 13 1415 SI MSB 50 or 06 MSB HIGH IMPENANCE 01 SO Figure 16: Enable Write Status Register (EWSR) or Write Enable (WREN) and Write Status Register (WRSR) Enter OTP Mode (ENSO) The ENSO (B1H) instruction is for entering the additional 4K bytes secured OTP mode. The additional 4K bytes secured OTP sector is independent from main array, which may use to store unique serial number for system identifier. User must unprotect whole array (BP0=BP1=BP2=0), prior to any Program operation in OTP sector. After entering the secured OTP mode, only the secured OTP sector can be accessed and user can only follow the Read or Program procedure with OTP address range (address bits [A23 -A12] must be "0"). The secured OTP data cannot be updated again once it is lock down or has been programmed. In secured OTP mode, WRSR command will ignore the input data and lock down the secured OTP sector (OTP_lock bit =1). To exit secured OTP mode, user must execute WRDI command. RES can be used to verify the secured OTP status as shown in Table 6. Figure 17: Enter OTP Mode (ENSO) Sequence Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2009 Revision: 1.4 19/33 ESMT OTP Sector Address Size 4K bytes Address Range 000000H ~ 000FFFH F25L16PA Note: The OTP sector is an independent Sector. Read-Electronic-Signature (RES) The RES instruction can be used to read the 8-bit Electronic Signature of the device on the SO pin. The RES instruction can provide access to the Electronic Signature of the device (except while an Erase, Program or WRSR cycle is in progress), Any RES instruction executed while an Erase, Program or WRSR cycle is in progress is no decoded, and has no effect on the cycle in progress. In OTP mode, user also can execute RES to confirm the status. Figure 18: Read-Electronic-Signature (RES) Table 6: Electronic Signature Data Command Mode Normal RES In secured OTP mode & non lock down (OTP_lock =0) In secured OTP mode & lock down (OTP_lock =1) Electronic Signature Data 14H 34H 74H Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2009 Revision: 1.4 20/33 ESMT JEDEC Read-ID The JEDEC Read-ID instruction identifies the device as F25L16PA and the manufacturer as ESMT. The device information can be read from executing the 8-bit command, 9FH. Following the JEDEC Read-ID instruction, the 8-bit manufacturer's ID, 8CH, is output from the device. After that, a 16-bit device ID is shifted out on the SO pin. Byte1, 8CH, identifies the manufacturer as ESMT. Byte2, 20H, identifies the memory type as SPI Flash. Byte3, 15H, identifies the device as F25L16PA F25L16PA. The instruction sequence is shown in Figure 19. The JEDEC Read ID instruction is terminated by a low to high transition on CE at any time during data output. If no other command is issued after executing the JEDEC Read-ID instruction, issue a 00H (NOP) command before going into Standby Mode ( CE =VIH). Figure 19: JEDEC Read ID Sequence Table 7: JEDEC Read-ID Data Device ID Memory Type (Byte 2) 20H Memory Capacity (Byte 3) 15H Manufacturer's ID (Byte 1) 8CH Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2009 Revision: 1.4 21/33 ESMT Read-ID (RDID) The Read-ID instruction (RDID) identifies the devices as F25L16PA and manufacturer as ESMT. This command is backward compatible to all ESMT SPI devices and should be used as default device identification when multiple versions of ESMT SPI devices are used in one design. The device information can be read from executing an 8-bit command, 90H, followed by address bits [A23 -A0]. Following the Read-ID F25L16PA instruction, the manufacturer's ID is located in address 00000H and the device ID is located in address 00001H. Once the device is in Read-ID mode, the manufacturer's and device ID output data toggles between address 00000H and 00001H until terminated by a low to high transition on CE . Figure 20: Read ID Sequence Table 8: Product ID Data Address 00000H Byte1 8CH Manufacturer's ID 14H 00001H Device ID ESMT F25L16PA Byte2 14H Device ID ESMT F25L16PA 8CH Manufacturer's ID Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2009 Revision: 1.4 22/33 ESMT ELECTRICAL SPECIFICATIONS F25L16PA Absolute Maximum Stress Ratings (Applied conditions are greater than those listed under "Absolute Maximum Stress Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this datasheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to +150C D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0V to VDD+2.0V Package Power Dissipation Capability (TA = 25C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W Surface Mount Lead Soldering Temperature (3 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240C Output Short Circuit Current (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA ( Note 1: Output shorted for no more than one second. No more than one output shorted at a time. ) AC CONDITIONS OF TEST Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ns Output Load . . . . . . . . . . . . . . . . . . . . . . . . CL = 15 pF for 75MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .CL = 30 pF for 50MHz See Figures 25 and 26 OPERATING RANGE Parameter Operating Supply Voltage Ambient Operating Temperature Symbol VDD (for FCLK 50MHz) VDD (for FCLK = 100MHz) TA Value 2.7 ~ 3.6 3.0 ~3.6 0 ~ 70 Unit V Table 9: DC OPERATING CHARACTERISTICS Symbol IDDR1 IDDR2 IDDR3 IDDW ISB ILI ILO VIL VIH VOL VOH Parameter Read Current Standard @33 MHz Dual Standard Read Current @ 50MHz Dual Read Current Standard @ 100MHz Dual Program and Erase Current Standby Current Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Min Limits Max 15 18 20 23 25 28 35 30 1 1 0.8 0.7 x VDD 0.2 VDD-0.2 Unit mA mA mA mA A A A V V V V Test Condition CE =0.1 VDD/0.9 VDD, SO=open CE =0.1 VDD/0.9 VDD, SO=open CE =0.1 VDD/0.9 VDD, SO=open CE =VDD CE =VDD, VIN =VDD or VSS VIN=GND to VDD, VDD=VDD Max VOUT=GND to VDD, VDD=VDD Max VDD=VDD Min VDD=VDD Max IOL=100 A, VDD=VDD Min IOH=-100 A, VDD=VDD Min Table 10: LATCH UP CHARACTERISTIC Symbol ILTH1 Parameter Latch Up Minimum 100 + IDD Unit mA Test Method JEDEC Standard 78 Note 1: This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2009 Revision: 1.4 23/33 ESMT Table 11: RECOMMENDED SYSTEM POWER-UP TIMINGS Symbol TPU-READ1 TPU-WRITE1 VDD Min to Read Operation VDD Min to Write Operation Parameter Minimum 10 10 F25L16PA Unit s s Table 12: CAPACITANCE (TA = 25C, f=1 MHz, other pins open) Parameter COUT1 CIN1 Output Pin Capacitance Input Capacitance Description Test Condition VOUT = 0V VIN = 0V Maximum 12 pF 6 pF Note 1: This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. Table 13: AC OPERATING CHARACTERISTICS Normal 33MHz Symbol FCLK TSCKH TSCKL TCES 1 Fast 50 MHz Fast 100 MHz Unit Min Max 50 9 9 5 5 5 5 100 5 5 5 5 5 5 100 9 0 3 3 5 5 5 5 0 3 3 5 5 5 5 9 9 0 0 8 7 9 9 9 Min Max 100 MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Parameter Min Serial Clock Frequency Serial Clock High Time Serial Clock Low Time CE Active Setup Time CE Active Hold Time CE Not Active Setup Time CE Not Active Hold Time CE High Time CE High to High-Z Output SCK Low to Low-Z Output Data In Setup Time Data In Hold Time HOLD Low Setup Time HOLD High Setup Time HOLD Low Hold Time HOLD High Hold Time HOLD Low to High-Z Output HOLD High to Low-Z Output Output Hold from SCK Change Output Valid from SCK 0 12 0 3 3 5 5 5 5 9 9 13 13 5 5 5 5 100 9 Max 33 TCEH1 TCHS1 TCHH1 TCPH TCHZ TCLZ TDS TDH THLS THHS THLH THHH THZ TLZ TOH TV Note 1: Relative to SCK. Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2009 Revision: 1.4 24/33 ESMT ERASE AND PROGRAMMING PERFORMANCE Limit Parameter Sector Erase Time Block Erase Time Chip Erase Time Byte Programming Time ( for AAI program ) Page Programming Time Byte Programming Time - 1st byte4 ( for page program ) Byte Programming Time - after 1st byte4 ( for page program ) Chip Programming Time Erase/Program Cycles1 Data Retention Notes: Symbol Typ TSE TBE TCE TBP TPP TBP1 90 1 10 7 1.5 100 2 F25L16PA Max3 200 2 30 30 5 150 Unit ms s s us ms us TBP2 6 50 100,000 20 12 100 - us s Cycles Years 1. Not 100% Tested, Excludes external system level over head. 2. Typical values measured at 25C, 3V. 3. Maximum values measured at 85C, 2.7V. 4. For multiple bytes after first byte within a page, TBPN = TBP1 + TBP2 *N (typical) and TBPN = TBP1 + TBP2 *N (max), where N = number of bytes programmed. TBP1 (typical) is also the recommended delay time before reading the status register after issuing a page program instruction. Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2009 Revision: 1.4 25/33 ESMT F25L16PA Figure 21: Serial Input Timing Diagram Figure 22: Serial Output Timing Diagram Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2009 Revision: 1.4 26/33 ESMT F25L16PA Figure 23: HOLD Timing Diagram VCC VCC (max) Program, Erase and Write command is ignored CE must track VCC VCC (min) Reset State VWI TPUW TVSL Read command is allowed Device is fully accessible Time Figure 24: Power-Up Timing Diagram Table 14: Power-Up Timing and VWI Threshold Parameter VCC(min) to CE low Time Delay before Write instruction Write Inhibit Threshold Voltage Note: These parameters are characterized only. Symbol TVSL TPUW VWI 1 Min. 200 10 2 Max. Unit us ms V Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2009 Revision: 1.4 27/33 ESMT Input timing reference level 0.8VCC 0.7VCC 0.3VCC AC Measurement Level F25L16PA Output timing reference level 0.5VCC 0.2VCC Note : Input pulse rise and fall time are <5ns Figure 25: AC Input / Output Reference Waveforms Figure 26: A Test Load Example Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2009 Revision: 1.4 28/33 ESMT PACKAGING DIMENSIONS 8-LEAD SOIC ( 150 mil ) F25L16PA 8 5 E H GAUGE PLANE 0.25 0 L DETAIL "X" 1 4 b D e A2 A SEATING PLANE Dimension in mm Symbol Min A A1 A2 b c H 1.35 0.10 1.25 0.33 0.19 5.80 Norm 1.60 0.15 1.45 0.406 0.203 6.00 Max 1.75 0.25 1.55 0.51 0.25 6.20 Dimension in inch Symbol Min 0.053 0.004 0.049 0.013 0.0075 0.228 Norm 0.063 0.006 0.057 0.016 0.008 0.236 Max 0.069 0.010 0.061 0.020 0.010 0.244 D E L e L1 A1 "X" L1 Dimension in mm Min 4.80 3.80 0.40 Norm 4.90 3.90 0.66 1.27 BSC 1.00 1.05 --1.10 8 Max 5.00 4.00 0.86 Dimension in inch Min 0.189 0.150 0.016 Norm 0.193 0.154 0.026 0.050 BSC 0.039 0.041 --0.043 8 Max 0.197 0.157 0.034 0 0 Controlling dimension : millimenter Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2009 Revision: 1.4 29/33 C ESMT PACKING DIMENSIONS 8-LEAD SOIC 200 mil ( official name - 209 mil ) F25L16PA 8 5 E1 1 b e 4 D A2 A E L A1 L1 SEATING PLANE DETAIL "X" Dimension in mm Symbol Min A A1 A2 b c D --0.05 1.70 0.36 0.19 5.13 Norm --0.15 1.80 0.41 0.20 5.23 Max 2.16 0.25 1.91 0.51 0.25 5.33 Dimension in inch Symbol Min --0.002 0.067 0.014 0.007 0.202 Norm --0.006 0.071 0.016 0.008 0.206 Max 0.085 0.010 0.075 0.020 0.010 0.210 E E1 L e L1 Dimension in mm Min 7.70 5.18 0.50 Norm 7.90 5.28 0.65 1.27 BSC 1.27 1.37 --1.47 8 Max 8.10 5.38 0.80 Dimension in inch Min 0.303 0.204 0.020 Norm 0.311 0.208 0.026 0.050 BSC 0.050 0.054 --0.058 8 Max 0.319 0.212 0.032 0 0 Controlling dimension : millimenter Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2009 Revision: 1.4 30/33 ESMT PACKING DIMENSIONS 8-LEAD P-DIP ( 300 mil ) D 8 5 0 E1 eB S e a t in g P la n e A1 L F25L16PA 1 4 A2 b 1 b e Symbol A A1 A2 D E E1 L e eB b b1 O Dimension in mm Min Norm Max 5.00 0.38 3.18 9.02 3.30 9.27 7.62 BSC. 6.22 9.02 6.35 9.27 2.54 TYP. 8.51 9.02 0.46 TYP. 1.52 TYP. 0 O A E Dimension in inch Min Norm Max 0.21 0.015 3.43 10.16 0.125 0.355 0.130 0.365 0.300 BSC. 0.135 0.400 6.48 10.16 0.245 0.115 0.250 0.130 0.100 TYP. 0.255 0.150 9.53 0.335 0.355 0.018 TYP. 0.060 TYP. 0.375 7 O 15 O 0 O 7O 15O Controlling dimension : Inch. Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2009 Revision: 1.4 31/33 ESMT Revision History Revision 1.0 1.1 1.2 Date 2008.02.25 2008.03.18 2008.07.17 Original 1. Add PDIP package. 2. Add TBP1 and TBP2. 1. Add Dual Output function 2. Add power-up timing specification 3. Add Revision History 4. Modify tSE timing 1.Modify headline 2.Correct chip erase time of feature 3.Correct typo error 4.Delete the rating of Temperature Under Bias 1.Add 8 lead SOIC (150 mil) package 2.Modify the description of OTP mode Description F25L16PA 1.3 1.4 2009.03.10 2009.07.20 Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2009 Revision: 1.4 32/33 ESMT Important Notice All rights reserved. F25L16PA No part of this document may be reproduced or duplicated in any form or by any means without the prior permission of ESMT. The contents contained in this document are believed to be accurate at the time of publication. ESMT assumes no responsibility for any error in this document, and reserves the right to change the products or specification in this document without notice. The information contained herein is presented only as a guide or examples for the application of our products. No responsibility is assumed by ESMT for any infringement of patents, copyrights, or other intellectual property rights of third parties which may result from its use. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of ESMT or others. Any semiconductor devices may have inherently a certain rate of failure. To minimize risks associated with customer's application, adequate design and operating safeguards against injury, damage, or loss from such failure, should be provided by the customer when making application designs. ESMT's products are not authorized for use in critical applications such as, but not limited to, life support devices or system, where failure or abnormal operation may directly affect human lives or cause physical injury or property damage. If products described here are to be used for such kinds of application, purchaser must do its own quality assurance testing appropriate to such applications. Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2009 Revision: 1.4 33/33 |
Price & Availability of F25L16PA
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |